`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:40:07 12/01/2020 
// Design Name: 
// Module Name:    MEM_WB 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////


module MEM_WB(
    input clk,
    input reset,
	 input [31:0] PCIn,
    input [31:0] instructionIn,
    input [31:0] dataToGRFIn,
	 input zeroIn,
	 output reg[31:0] PCOut,
    output reg[31:0] instructionOut,
    output reg[31:0] dataToGRFOut,
	 output reg zeroOut
    );
	always @(posedge clk)begin
		if(reset)begin
			instructionOut <= 0;
			dataToGRFOut <= 0;
			PCOut <= 0;
			zeroOut <= 0;
		end
		else begin
			PCOut <= PCIn;
			instructionOut <= instructionIn;
			dataToGRFOut <= dataToGRFIn;
			zeroOut <= zeroIn;
		end		
	end

endmodule
